Energy Efficient Cortex-M0+ Processor
Sponsored Product Highlight
Posted Oct 24th 2013
An optimized architecture with a core pipeline of just two stages, enables the Cortex-M0+ processor to achieve a power consumption of just 9.8µW/MHz (90LP process, minimal configuration), while raising the performance to 2.15 CoreMark/MHz.
The Cortex-M0+ processor keeps the same 56 instructions of the Cortex-M0 processor, enabling simple and quick development. The Thumb® instruction set offers an unrivaled code-density while providing access to 32-bit computation performance. The combination of these features make the Cortex-M0+ processor a natural and cost effective successor to 8/16-bit devices in a wide variety of applications, while retaining tool and binary upwards compatibility with the feature-rich Cortex-M3 and Cortex-M4 processors.
Features
- ISA Support: Thumb / Thumb-2 subset
- Pipeline: 2 stage
- Performance Efficiency: 2.42 CoreMarks/MHz
- Performance Efficiency: 0.93 / 1.08 / 1.31 DMIPS/MHz
- Memory Protection: Optional 8 region MPU with sub regions and background region
- Interrupts: Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts
- Sleep Modes:
- Integrated WFI and WFE Instructions and Sleep On Exit capability
- Sleep & Deep Sleep Signals
- Optional Retention Mode with ARM Power Management Kit - Bit Manipulation: Bit banding region can be implemented with Cortex-M System Design Kit
- Enhanced Instructions: Hardware single-cycle (32×32) multiply option
- Debug: Optional JTAG or Serial-Wire Debug Ports Up to 4 Breakpoints and 2 Watchpoints
- Trace: Optional Micro Trace Buffer
4K-bit FRAM LSI with Serial Interface
Sponsored Product Highlight
Posted Oct 24th 2013
MB85RC04V is a 4K-bit FRAM LSI with serial interface, using the ferroelectric process and CMOS process technologies for forming the nonvolatile memory cells. Because FRAM is able to write high-speed even though a nonvolatile memory, it is suitable for the log management and the storage of the resume data, and many others.
The MB85RC04V is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 512 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells.
The MB85RC04V has the two-wire serial interface (I2C bus) and operates as a slave device. The I2C bus defines communication roles of “master” and “slave” devices, with the master side holding the authority to initiate control. Furthermore, the I2C bus connection is possible where a single master device is connected to multiple slave devices in a party-line configuration. In this case, it is necessary to assign a unique device address to the slave device, the master side starts communication after specifying the slave to communicate by addresses.
Features
- Bit configuration at 512 words × 8 bits
- Two-wire serial interface (Fully controllable by two ports)
- Operating frequency at 1 MHz (Max)
- Read/write endurance at 1012 times/byte
- Data retention at 10 years (+85°C), 95 years (+55°C), over 200 years (+35 °C)
- Operating power supply voltage ranges from 3 V to 5.5V
- Low power consumption
- RoHS Compliant Package
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